1. Field of Invention
The present invention generally relates to a silicon wafer, and in particular, to a wafer technology that is preferably applied to an epitaxial silicon wafer for an integrated circuit element of a semiconductor.
2. Description of the Related Art
A trend of increase in an integration level of an integrated circuit element (i.e., device) of a silicon semiconductor has rapidly progressed, and demands for the quality of a silicon wafer on which the device is to be formed has been getting stricter increasingly. Specifically, in association with the increase in the integration level, the integrated circuit becomes more minute in its scale. Due to this, in an area where the device is to be formed, or so-called, a device active region, a crystal defect, such as dislocation, and a metallic impurity are strictly inhibited. This is because those may cause an increased leak current and a reduced lifetime of carriers.
In recent years, a power semiconductor device has been used in an application of controlling a power supply. As a substrate for the power semiconductor device has been primarily used an epitaxial silicon wafer made of a silicon wafer obtained by slicing a silicon single crystalline ingot grown by the Czochralski (CZ) method, on which surface a silicon epitaxial layer containing substantially no crystal defect has been grown. This silicon wafer generally has been doped with a dopant in a high concentration.
There is a further demand in the power semiconductor device for providing a silicon wafer having a low resistivity aiming for achieving further reduced electric power consumption. For the silicon wafer of n-type, the silicon wafer having the resistivity of 0.002 Ωcm may be fabricated by doping it with arsenic (As) representative of an N-type dopant in a high concentration. Further, for the silicon wafer of p-type, boron (B) representative of a p-type dopant is used for doping to thereby form a substrate of the p-type epitaxial wafer.
However, in association with the silicon epitaxial layer grown on the surface of the silicon wafer having the resistivity especially not higher than 0.003 Ωcm, a miss-fit dislocation is induced within the epitaxial silicon wafer resultant from a difference between a lattice constant of the silicon wafer and a lattice constant of the silicon epitaxial layer. This miss-fit dislocation is shifted to the surface of the silicon epitaxial layer during the epitaxial growth, and thus the dislocation could appear in the device active region on which the semiconductor device is to be fabricated. In this way, if such a dislocation representing the crystal defect exists in the silicon epitaxial layer, it would be a factor in causing malfunctioning of the device and resultantly deteriorate a yield of nondefective product.
To solve the problems described above, there has been proposed such a prior art method as disclosed, for example, in U.S. Pat. No. 4,769,689, in which a silicon wafer doped with boron (B) is further doped with germanium (Ge). According to this method, by doping the silicon wafer with boron and germanium so as to satisfy the relational expression defined by [Ge]=8[B], the difference between the lattice constant of the silicon wafer doped with boron of no smaller than 0.002% (resistivity of no greater than 0.015 Ωcm) and the lattice constant of the silicon epitaxial layer may be cancelled thus to reduce the occurrences of the miss-fit dislocation. In the above expression, the [B] represents a boron concentration, while the [Ge] represents a germanium concentration.
However, if the CZ method is employed as the method for growing the silicon single crystal, owing to the fact that a segregation constant of boron is different from that of germanium, it will be impossible for all of the crystalline regions (throughout the crystal length) of the silicon crystal to grow while always satisfying the relation defined by above expression [Ge]=8[B]. Further, if high concentration of doping with boron were applied in order to reduce the resistivity of the silicon wafer, the doping volume required for germanium would be enormous. For example, assuming that the weight of the silicon of liquid phase is 35 kg for the boron concentration of 3.6×1019 atoms/cm3 (resistivity 0.003 Ωcm). Then, the necessary germanium amount should be 1.5 kg. Since germanium is very expensive, manufacturing cost of the silicon wafer would be increased. Further, according to the study by the inventors, it has been found that if boron is added in high concentration and at the same time germanium is used for doping also in the high concentration, then the probability of first dislocation generation of the silicon single crystal during the growing of the silicon single crystal could be higher, leading to the deterioration of the crystal yield in manufacturing of the silicon single crystalline ingot.